Computer systems of the PC type usually employ a so-called expansion bus to handle various data transfers and transactions related to I/O and disk access. The expansion bus is separate from the system bus or from the bus to which the processor is connected, but is coupled to the system bus by a bridge circuit.
For some time, all PC's employed the ISA (Industry Standard Architecture) expansion bus, which was an 8-Mhz, 16-bit device (actually clocked at 8.33 Mhz). Using two cycles of the bus clock to complete a transfer, the theoretical maximum transfer rate was 8.33 Mbytes/sec. Next, the EISA (Extension to ISA) bus was widely used, this being a 32-bit bus clocked at 8-Mhz, allowing burst transfers at one per clock cycle, so the theoretical maximum was increased to 33 Mbytes/sec. As performance requirements increased, with faster processors and memory, and increased video bandwidth needs, a high performance bus standard was a necessity. Several standards were proposed, including a Micro Channel architecture which was a 10-Mhz, 32-bit bus, allowing 40 MByte/sec, as well as an enhanced Micro Channel using a 64-bit data width and 64-bit data streaming, theoretically permitting 80-to-160 Mbyte/sec transfer. The requirements imposed by the use of video and graphics transfer on networks, however, necessitate even faster transfer rates. One approach was the VESA (Video Electronics Standards Association) bus which was a 33 Mhz, 32-bit local bus standard specifically for a 486 processor, providing a theoretical maximum transfer rate of 132 Mbyte/sec for burst, or 66 Mbyte/sec for non-burst; the 486 had limited burst transfer capability. The VESA bus was a short-term solution as higher-performance processors, e.g., the Intel P5 and P6 or Pentium and Pentium Pro processors, became the standard.
The PCI (Peripheral Component Interconnect) bus was proposed by Intel as a longer-term solution to the expansion bus standard, particularly to address the burst transfer issue. The original PCI bus standard has been upgraded several times, with the current standard being Revision 2.1, available from a trade association group referred to as PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214. The PCI Specification, Rev. 2.1, is incorporated herein by reference. Construction of computer systems using the PCI bus, and the PCI bus itself, are described in many publications, including "PCI System Architecture," 3rd Ed., by Shanley et al., published by Addison-Wesley Pub. Co., also incorporated herein by reference. The PCI bus provides for 32-bit or 64-bit transfers at 33- or 66-Mhz; it can be populated with adapters requiring fast access to each other and/or with system memory, and that can be accessed by the host processor at speeds approaching that of the processor's native bus speed. A 64-bit, 66-MHz PCI bus has a theoretical maximum transfer rate of 528 MByte/sec. All read and write transfers over the bus can be burst transfers. The length of the burst can be negotiated between initiator and target devices, and can be any length.
System and component manufacturers have implemented PCI bus interfaces in various ways. For example, Intel Corporation manufactures and sells a PCI Bridge device under the part number 82450GX, which is a single-chip host-to-PCI bridge, allowing CPU-to-PCI and PCI-to-CPU transactions, and permitting up to four P6 processors and two PCI bridges to be operated on a system bus. Another example, offered by VLSI Technology, Inc., is a PCI chipset under the part number VL82C59x SuperCore, providing logic for designing a Pentium based system that uses both PCI and ISA buses. The chipset includes a bridge between the host bus and the PCI bus, a bridge between the PCI bus and the ISA bus, and a PCI bus arbiter. Posted memory write buffers are provided in both bridges, and provision is made for Pentium's pipelined bus cycles and burst transactions.
The "Pentium Pro" processor, commercially available from Intel Corporation uses a processor bus structure as defined in the specification for this device, particularly as set forth in the publication "Pentium Pro Family Developer's Manual" Vols. 1-3, Intel Corp., 1996, available from McGraw-Hill, and incorporated herein by reference; this manual is also available from Intel by accessing &lt;http://www.intel.com&gt;.
A CPU operates at a much faster clock rate and data access rate than most of the resources it accesses via a bus. In earlier processors, such as those commonly available when the ISA bus and EISA bus were designed, this delay in reading data from a resource on the bus was handled by wait states. When a processor requested data that was not immediately available due to a slow memory or disk access, then the processor merely marked time using wait states, doing no useful work, until the data finally became available. In order to make use of this delay time, a processor such as the P6 provides a pipelined bus that allows multiple transactions to be pending on the bus at one time, rather than requiring one transaction to be finished before starting another. Also, the P6 bus allows split transactions, i.e., a request for data may be separated from the delivery of the data by other transactions on the bus. The P6 processor uses a technique referred to as a "deferred transaction" to accomplish the split on the bus. In a deferred transaction, a processor sends out a read request, for example, and the target sends back a "defer" response, meaning that the target will send the data onto the bus, on its own initiative, when the data becomes available. Another transaction available on the P6 bus is a "retry" response. If a target is not able to supply a requested item, the target may respond to the request from the processor using a retry signal, and in that case the processor will merely send the request again the next time it has access to the bus.
The PCI bus specification as set forth above does not provide for split transactions. There is no mechanism for issuing a "deferred transaction" signal, nor for generating the deferred data initiative. Accordingly, while a P6 processor can communicate with resources such as main memory that are on the processor bus itself using deferred transactions, this technique is not employed when communicating with disk drives, network resources, compatibility devices, etc., on an expansion bus.
Many manufacturers of computer equipment and associated components have committed to the goal of achieving low power consumption in accordance with environmental concerns. The Pentium family of processors made by Intel Corporation has significantly higher power usage. At least in part to improve power consumption, Pentium processors have a system management mode. In this mode, a system can be powered down in appropriate situations to conserve power.
One issue that arises with the system management mode involves the effect that entering the system management mode might have on transactions which were being processed when the system management interrupt was issued. In addition, some system memory may be overlaid by the memory used in the system management mode. Therefore, the Pentium processor normally delays entering the system management mode until all processor implemented transfers to external memory, including buffered write operations, have been completed. This is accomplished by delaying the assertion of the signal "SMIACT#," which results in entry into the system management mode, until sometime after the system management interrupt signal is recognized by the processor. The delay is sufficient to enable all of the transfers to external memory to be completed. The system processor may also wait for a signal to be asserted indicating that all external buffers have also been flushed to memory. This ensures that the data in write buffers is written to normal memory, not to the system management mode memory.
With the advent of increasingly complex computer systems implemented with microprocessors, increasingly complex computer architectures are now commonly being used. In such architectures, more than one bus is commonly used in a given computer system with one or more bridges which connect buses to one another. The multi-bus architecture can significantly increase the capability of a single computer system.
One function that many bridges accomplish is the implementation of posted memory write buffers. The posted memory write buffers increase the performance of a bus master on one bus that writes through the bridge to memory on another bus.
Consider, for example, a bridge that currently has posted write data to be transferred from a first side of the bridge to the second side when a memory write is detected on the second side of the bridge. The bridge can accept and post the write data being presented by the initiator on the first side without the need to flush the posted writes from the second side. Thus, the implementation of posted memory write buffers may be extremely advantageous to the efficient operation of computer systems.
However, the use of posted memory write buffers is not necessarily consistent with the implementation of a system management mode feature. Both system management mode and posted write buffers are currently authorized by existing industry specifications. However, the possibility exists that when an agent enters the system management mode, write operations currently situated in posted memory write buffers in bridges may not be accounted for. As a result, devices on a particular bus may actually interpret write operations occurring after the initial system management as system management write operations when, in fact, they are the result of posted writes which continue to be processed from the bridge. The results can be troublesome especially since, as described above, the system management mode and normal operations may use overlapping memory regions.
Thus, a computer system that is capable of implementing both posted memory write buffers in bridges and a system management mode, without a faulty operation, would be extremely desirable. Such a system would not only facilitate power savings and the other features of the system management mode, but would achieve the operating efficiencies available from posted memory write buffers.